Name
Abstract | ||
|---|---|---|
Future systems are expected to increasingly include a Non-Volatile Main Memory (NVMM). However, due to the limited NVMM write endurance, the number of writes must be reduced. While new architectures and algorithms have been proposed to reduce writes to NVMM, few or no studies have looked at the effect of compiler optimizations on writes.In this paper, we investigate the impact of one popular compiler optimization (loop tiling) on a very important computation kernel (matrix multiplication). Our novel observation includes that tiling on matrix multiplication causes a 25× write amplification. Furthermore, we investigate techniques to make tilling more NVMM friendly, through choosing the right tile size and employing hierarchical tiling. Our method Write-Efficient Tiling (WET) adds a new outer tile designed for fitting the write working set to the Last Level Cache (LLC) to reduce the number of writes to NVMM. Our experiments reduce writes by 81% while simultaneously improve performance. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/DAC18072.2020.9218612 | 2020 57th ACM/IEEE Design Automation Conference (DAC) |
DocType | ISSN | ISBN |
Conference | 0738-100X | 978-1-7281-1085-1 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohammad A. Alshboul | 1 | 14 | 3.26 |
| James Tuck | 2 | 564 | 33.06 |
| Yan Solihin | 3 | 2057 | 111.56 |