| Horus: Persistent Security for Extended Persistence-Domain Memory Systems | 0 | 0.34 | 2022 |
| BBB: Simplifying Persistent Programming using Battery-Backed Buffers | 2 | 0.39 | 2021 |
| WET: Write Efficient Loop Tiling for Non-Volatile Main Memory | 0 | 0.34 | 2020 |
| Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory | 1 | 0.35 | 2019 |
| Lazy Persistency: A High-Performing and Write-Efficient Software Persistency Technique. | 2 | 0.35 | 2018 |
| Hardware Supported Permission Checks on Persistent Objects for Performance and Programmability. | 0 | 0.34 | 2018 |
| Efficient Checkpointing of Loop-Based Codes for Non-volatile Main Memory | 7 | 0.46 | 2017 |
| Improving the effectiveness of searching for isomorphic chains in superword level parallelism. | 2 | 0.36 | 2017 |
| Hiding the Long Latency of Persist Barriers Using Speculative Execution. | 7 | 0.41 | 2017 |
| Hardware supported persistent object address translation. | 6 | 0.42 | 2017 |
| Proteus: a flexible and fast software supported hardware logging approach for NVM. | 17 | 0.61 | 2017 |
| Lightweight runtime checking of C programs with RTC. | 2 | 0.36 | 2016 |
| Runtime checking C programs | 1 | 0.34 | 2015 |
| Automatic parallelization of fine-grained metafunctions on a chip multiprocessor | 3 | 0.44 | 2013 |
| HiRe: using hint & release to improve synchronization of speculative threads | 0 | 0.34 | 2012 |
| Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era | 17 | 1.05 | 2012 |
| Efficient and accurate data dependence profiling using software signatures | 6 | 0.45 | 2012 |
| HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor | 8 | 0.45 | 2011 |
| Memory management thread for heap allocation intensive sequential applications | 3 | 0.46 | 2009 |
| SoftSig: software-exposed hardware signatures for code analysis and optimization | 3 | 0.46 | 2009 |
| The Bulk Multicore architecture for improved programmability | 20 | 0.80 | 2009 |
| BulkSC: bulk enforcement of sequential consistency | 119 | 3.56 | 2007 |
| CAP: Criticality analysis for power-efficient speculative multithreading | 6 | 0.43 | 2007 |
| CAVA: Using checkpoint-assisted value prediction to hide L2 misses | 20 | 0.90 | 2006 |
| POSH: a TLS compiler that exploits program structure | 112 | 3.11 | 2006 |
| Scalable Cache Miss Handling for High Memory-Level Parallelism | 19 | 1.17 | 2006 |
| Energy-Efficient Thread-Level Speculation | 12 | 3.18 | 2006 |
| Thread-Level Speculation on a CMP can be energy efficient | 23 | 0.88 | 2005 |
| Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation | 57 | 2.10 | 2005 |
| CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction | 8 | 0.71 | 2004 |
| Handling crosscutting constraints in domain-specific modeling | 81 | 7.50 | 2001 |
