Name
Abstract | ||
|---|---|---|
Semiconductor design companies are integrating proprietary intellectual property (IP) blocks to build custom integrated circuits (ICs) and fabricate them in a third-party foundry. Unauthorized IC copies cost these companies billions of dollars annually. While several methods have been proposed for hardware IP obfuscation, they operate on the gate-level netlist, i.e., after the synthesis tools embed most of the semantic information into the netlist. We propose ASSURE to protect hardware IP modules operating on the register-transfer level (RTL) description. The RTL approach has three advantages: 1) it allows designers to obfuscate IP cores generated with many different methods (e.g., hardware generators, high-level synthesis tools, and preexisting IPs); 2) it obfuscates the semantics of an IC before logic synthesis; and 3) it does not require modifications to EDA flows. We perform a cost and security assessment of ASSURE against state-of-the-art oracle-less attacks. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TVLSI.2021.3074004 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | DocType | Volume |
IP protection,logic locking,register-transfer level (RTL),untrusted foundry | Journal | 29 |
Issue | ISSN | Citations |
7 | 1063-8210 | 1 |
PageRank | References | Authors |
0.35 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christian Pilato | 1 | 329 | 32.19 |
| Animesh Basak Chowdhury | 2 | 1 | 0.35 |
| D. Sciuto | 3 | 448 | 43.67 |
| Siddharth Garg | 4 | 675 | 55.14 |
| Ramesh Karri | 5 | 2968 | 224.90 |