Name
Abstract | ||
|---|---|---|
Due to the rapid technology scaling and increasing program/erase cycling, the raw bit error rate (RBER) in NAND flash memory keeps increasing rapidly. Conventional error correction codes (ECCs) with stronger protection capability are usually equipped for all flash pages as a solution to maintain the mandatory yield and reliability levels. However, the growth of RBER induced by increasing P/E cycles will lead to uneven distribution of errors. Applying uniform ECC protection capability for all flash pages might incur unnecessary hardware and latency overhead. Moreover, the overlong ECC check bits might be stored in two different flash pages. Therefore, two flash reads are required to retrieve a codeword. In this paper, ECC caching (E
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup>
C) techniques are proposed to cure these drawbacks of conventional uniform protection techniques. The main idea is to upgrade the ECC protection levels for flash pages when their correction slack is below the specified threshold. According to experimental results, we can enhance the reliability of flash memories significantly with negligible hardware cost. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ITC-Asia51099.2020.00020 | 2020 IEEE International Test Conference in Asia (ITC-Asia) |
DocType | ISBN | Citations |
Conference | 978-1-7281-8944-4 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shyue-Kung Lu | 1 | 259 | 34.09 |
| Zeng-Long Tsai | 2 | 0 | 0.68 |
| Chun-Lung Hsu | 3 | 59 | 14.53 |
| Chi-Tien Sun | 4 | 0 | 1.69 |