Paper Info
Title
DEPS: Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD
Abstract
3-D NAND flash memory is gradually being widely used in solid state drives (SSDs), leading to increasing storage capacity. However, the read performance of SSD is sacrificed for decoding operations which are executed to guarantee the data reliability. No matter whether the data have bit errors, they will be sent to error correcting code (ECC) engine to decode, introducing a high read delay of SSD. Error prechecking can help to avoid the redundant decoding operations for the error-free data, but it induces extra checking overhead to the error data. Motivated by this, we carry out comprehensive experiments to analyze the distribution of bit errors in 3-D NAND flash memory. The preliminary experimental results show that there are a large number of pages read without errors in the early lifetime of 3-D NAND flash memory. Based on the observations and analyses, we propose a model to estimate the error-free ratio, and utilize it to design a dynamic error prechecking scheme (DEPS) to bypass the decoding operation for the error-free data in 3-D NAND flash memory and improve the read performance of SSD. Furthermore, by dividing a large page into small subpages, DEPS releases more error-free data, which significantly improves the read performance of SSD. Evaluation results from real-world traces demonstrate that by implementing DEPS, the average read performance of SSD is enhanced by 35%-55% with 3-D MLC NAND flash memory.
Year
DOI
Venue
2021
10.1109/TCAD.2020.2994266
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
DocType
Volume
3-D NAND flash memory,error prechecking,read performance,solid state drive (SSD)
Journal
40
Issue
ISSN
Citations 
1
0278-0070
1
PageRank 
References 
Authors
0.39
0
7
Name
Order
Citations
PageRank
Weihua Liu151.51
Fei Wu210435.76
Meng Zhang3165.23
Chengmo Yang430232.31
Zhonghai Lu51063100.12
Jiguang Wan6299.71
Changsheng Xie7329.93