Name
Abstract | ||
|---|---|---|
Placement for very large-scale integrated (VLSI) circuits is one of the most important steps for design closure. We propose a novel GPU-accelerated placement framework DREAMPlace, by casting the analytical placement problem equivalently to training a neural network. Implemented on top of a widely adopted deep learning toolkit PyTorch, with customized key kernels for wirelength and density computations, DREAMPlace can achieve around 40× speedup in global placement without quality degradation compared to the state-of-the-art multithreaded placer RePlAce. We believe this work shall open up new directions for revisiting classical EDA problems with advancements in AI hardware and software. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TCAD.2020.3003843 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Deep learning,GPU acceleration,physical desgin,VLSI placement | Journal | 40 |
Issue | ISSN | Citations |
4 | 0278-0070 | 6 |
PageRank | References | Authors |
0.44 | 0 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yibo Lin | 1 | 119 | 20.98 |
| Zixuan Jiang | 2 | 7 | 2.49 |
| Jiaqi Gu | 3 | 18 | 6.97 |
| Wuxi Li | 4 | 36 | 6.03 |
| Shounak Dhar | 5 | 32 | 4.84 |
| Haoxing Ren | 6 | 288 | 22.61 |
| Brucek Khailany | 7 | 1187 | 118.43 |
| David Z. Pan | 8 | 2653 | 237.64 |