Name
Abstract | ||
|---|---|---|
Statistical circuit analysis and optimization are critical for robust nanoscale design. To accurately perform such analysis, primary process variation sources need to be identified and modeled for further circuit simulation. In this work we present a rigorous method to extract process variations from in-situ IV measurements. Transistor statistics are collected from a test chip fabricated in a 65nm SOI process. We recognize gate length (L), threshold Voltage (V-th) and mobility (mu) as the leading variation sources, due to the tremendous process challenge in lithography, channel doping, and stress. To decompose them, only three IV points are needed from the leakage and linear regions. Both L and V-th variations are normally distributed, with negligible spatial correlation. By including extracted variations in the nominal model file, we can accurately predict the change of drive current in all process corners. The new extraction method guarantees excellent model matching with hardware for further statistical circuit analysis. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ESSCIRC.2007.4430253 | Proceedings of the European Solid-State Device Research Conference |
DocType | ISSN | Citations |
Conference | 1930-8876 | 0 |
PageRank | References | Authors |
0.34 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei Zhao | 1 | 314 | 28.64 |
| Yu Cao | 2 | 329 | 29.78 |
| Frank Liu | 3 | 262 | 23.05 |
| Kanak B. Agarwal | 4 | 328 | 28.02 |
| Dhruva Acharyya | 5 | 82 | 8.56 |
| Sani R. Nassif | 6 | 0 | 0.34 |
| Kevin J. Nowka | 7 | 184 | 22.64 |