Name
Title | ||
|---|---|---|
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm |
Abstract | ||
|---|---|---|
This paper presents an 11 bit fully dynamic pipelined ADC with an integrated reference buffer that consumes only 8% of total power. It operates from 1MS/s to 1GS/s and maintains 59.5dB SNDR and 14fJ/conv-step FoM
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across this range. Furthermore, a small circuit is introduced that provides background reconstruction of amplifier settling behavior. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/VLSICircuits18222.2020.9162788 | 2020 IEEE Symposium on VLSI Circuits |
Keywords | DocType | ISSN |
fully dynamic reference regulation,stochastic scope-on-chip background monitoring,pipelined ADC,integrated reference buffer,ring amp-based pipelined ADC,amplifier background reconstruction | Conference | 2158-5601 |
ISBN | Citations | PageRank |
978-1-7281-9943-6 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Benjamin P. Hershberg | 1 | 180 | 23.21 |
| Nereo Markulic | 2 | 52 | 9.29 |
| Jorge Lagos | 3 | 18 | 5.57 |
| Ewout Martens | 4 | 75 | 17.77 |
| Davide Dermit | 5 | 8 | 3.91 |
| Jan Craninckx | 6 | 756 | 181.43 |