Name
Title | ||
|---|---|---|
Instruction Sequence Identification and Disassembly Using Power Supply Side-Channel Analysis |
Abstract | ||
|---|---|---|
Embedded systems are prone to leak information via side-channels associated with their physical internal activity, such as power consumption, timing, and faults. Leaked information can be analyzed to extract sensitive data and devices should be assessed for such vulnerabilities. Side-channel power-supply leakage from embedded devices can also provide information regarding instruction-level activity for control code executed on these devices. Methods proposed to disassemble instruction-level activity via side-channel leakage have not addressed issues related to pipelined multi-clock-cycle architectures, nor have proven robustness or reliability. The problem of detecting malicious code modifications while not obstructing the sequence of instructions being executed needs to be addressed. In this article, instruction sequences being executed on a general-purpose pipelined computing platform are identified and instructions that make up these sequences are classified based on hardware utilization. Individual instruction classification results using a fine-grained classifier is also presented. A dynamic programming algorithm was applied to detect the boundaries of instructions in a sequence with a 100 percent accuracy. A unique aspect of this technique is the use of multiple power supply pin measurements to increase precision and accuracy. To demonstrate the robustness of this technique, power leakage data from ten target FPGAs programmed with a prototype of the pipelined architecture was analyzed and classification accuracies averaging 99 percent were achieved with instructions labeled based on hardware utilization. Individual instruction classification accuracies above 90 percent were achieved using a fine-grained classifier. Classification accuracies were also verified when a target FPGA was subjected to different controlled temperatures. The classification accuracies on discrete (ASIC) pipelined-architecture microcontrollers was 97 percent. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TC.2020.3018092 | IEEE Transactions on Computers |
Keywords | DocType | Volume |
Side-channel analysis,power analysis,hardware security,instruction disassembly | Journal | 69 |
Issue | ISSN | Citations |
11 | 0018-9340 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Deepak Krishnankutty | 1 | 0 | 1.01 |
| Zheng Li | 2 | 542 | 66.91 |
| Ryan Robucci | 3 | 70 | 12.38 |
| Nilanjan Banerjee | 4 | 1352 | 118.87 |
| Chintan Patel | 5 | 385 | 37.44 |