Name
Title | ||
|---|---|---|
Autonomous Application of Netlist Transformations inside Lagrangian Relaxation-based Optimization |
Abstract | ||
|---|---|---|
Timing closure is a complex process that involves many iterative optimization steps applied in various phases of the physical design flow. Lagrangian relaxation (LR)-based optimization has been established as a viable approach for this. We extend LR-based optimization by interleaving in each iteration various techniques, such as gate and flip-flop sizing, buffering to fix late and early timing vio... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TCAD.2020.3025541 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Logic gates,Delays,Clocks,Runtime,Cost function | Journal | 40 |
Issue | ISSN | Citations |
8 | 0278-0070 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Apostolos Stefanidis | 1 | 0 | 1.35 |
| Dimitrios Mangiras | 2 | 0 | 2.37 |
| Chrysostomos Nicopoulos | 3 | 835 | 50.37 |
| David Chinnery | 4 | 141 | 9.97 |
| Giorgos Dimitrakopoulos | 5 | 215 | 27.31 |