Name
Abstract | ||
|---|---|---|
Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the through-silicon vias (TSVs) defect tend to be clustered, reducing the yield of 3-D integrated circuit significantly. To tackle this fault clustering problem, the existing TSV repair methods adopt the TSV redundancy idea, which brings a major cost to 3-D integration. In this brief, a honeycomb-TDMA TSV design is proposed to mitigate the impact of multiple clustered faults without the need of redundant TSVs (RTSVs), thereby decreasing the area overhead and enhances the yield. The yield of the honeycomb-TDMA architecture can achieve 91.38%-99.67% for different benchmark circuits from IWLS 2005, which has the highest yield. Furthermore, our design achieves total additional hardware (timing delay overhead) reduction by 83.70%-86.85% (46.01%-55.96%), 66.89%-73.25% (29.41%-38.49%), 68.02%-74.20% (41.40%-52.20%), 60.60%-68.18% (18.09%-33.18%), and 75.86%-80.52% (3.05%-20.91%), respectively, compared with router-based, ring-based, group-based, cellular-based, and honeycomb-based methods. Therefore, the proposed architecture is the best choice in terms of yields, hardware overhead, and timing delay. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TCAD.2020.3025169 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
3-D integrated circuit (3D IC),honeycomb,through-silicon via (TSV),TDMA,yield | Journal | 40 |
Issue | ISSN | Citations |
9 | 0278-0070 | 1 |
PageRank | References | Authors |
0.36 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tianming Ni | 1 | 26 | 10.23 |
| Qi Xu | 2 | 74 | 16.05 |
| Zhengfeng Huang | 3 | 84 | 30.14 |
| Huaguo Liang | 4 | 216 | 33.27 |
| Aibin Yan | 5 | 29 | 6.78 |
| Xiaoqing Wen | 6 | 790 | 77.12 |