Name
Title | ||
|---|---|---|
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS |
Abstract | ||
|---|---|---|
In this work, we present a compute-in-memory (CIM) macro built around a standard two-port compiler macro using foundry 8T bit-cell in 7-nm FinFET technology. The proposed design supports 1024 4 b
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula>
4 b multiply-and-accumulate (MAC) computations simultaneously. The 4-bit input is represented by the number of read word-line (RWL) pulses, while the 4-bit weight is realized by charge sharing among binary-weighted computation caps. Each unit of computation cap is formed by the inherent cap of the sense amplifier (SA) inside the 4-bit Flash ADC, which saves area and minimizes kick-back effect. Access time is 5.5 ns with 0.8-V power supply at room temperature. The proposed design achieves energy efficiency of 351 TOPS/W and throughput of 372.4 GOPS. Implications of our design from neural network implementation and accuracy perspectives are also discussed. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/JSSC.2020.3031290 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
8T,compute-in-memory (CIM),multi-bit,SRAM,SRAM compiler | Journal | 56 |
Issue | ISSN | Citations |
1 | 0018-9200 | 3 |
PageRank | References | Authors |
0.41 | 10 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mahmut E. Sinangil | 1 | 70 | 8.03 |
| Burak Erbagci | 2 | 5 | 0.81 |
| Rawan Naous | 3 | 4 | 0.76 |
| Kerem Akarvardar | 4 | 4 | 0.76 |
| Dar Sun | 5 | 9 | 2.31 |
| Win-San Khwa | 6 | 29 | 5.14 |
| Hung-Jen Liao | 7 | 61 | 12.94 |
| Yih Wang | 8 | 3 | 1.09 |
| Jonathan Yung-Cheng Chang | 9 | 166 | 25.48 |