Name
Abstract | ||
|---|---|---|
Depthwise separable convolution is useful for building small and lightweight networks. However, the hardware design of depthwise separable convolution unit has not been well studied. With an analysis, we find that many multiplications in depthwise separable convolution can be omitted. Based on this observation, in this paper, we present a novel hardware design to avoid unnecessary multiplications (by using the clock gating technique) for power saving. Experiments on MobileNetV1 model show that the proposed hardware unit can greatly reduce power consumption. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ICCE-Taiwan49838.2020.9258173 | 2020 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-Taiwan) |
Keywords | DocType | ISSN |
Convolution,Clock Gating,Digital Design,Logic Circuits,Neural Networks | Conference | 2575-8276 |
ISBN | Citations | PageRank |
978-1-7281-7400-6 | 0 | 0.34 |
References | Authors | |
1 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shi-Rou Lin | 1 | 0 | 0.34 |
| Wei-Hung Lin | 2 | 0 | 0.68 |
| Shih-Hsu Huang | 3 | 203 | 38.89 |
| Chun-Lung Hsu | 4 | 59 | 14.53 |
| Chitien Sun | 5 | 0 | 0.34 |