Title
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS
Abstract
This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with a proposed residue transformation method to control the residue generation of the first stages in two fine channels. The residue voltages generate on the capacitive digital-to-analog converters (C-DACs) of split fine channels directly without successive approximation processes. Therefore, the conversion rate is increased and the power is reduced. A shuffle mechanism is introduced into split-ADC based digital background calibration to avoid the divergence of the conventional algorithm in the proposed architecture. A high-energy-efficiency dynamic amplifier is also introduced as the residue amplifier. A 14-bit 60-MS/s ADC is prototyped in a 28-nm CMOS process. The digital calibration engine operates under 0.9-V supply, other parts of the ADC core operate under 1.05-V supply. The ADC core consumes 4.26 mW. Measurement results show that the calibration improved the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) dramatically, the calibrated ADC achieves SNDR and SFDR of 66.9 dB and of 91.0 dB respectively, translating to a Schreier FoM of 165.4 dB and a Walden FoM of 39.3 fJ/conversion-step.
Year
DOI
Venue
2021
10.1109/TCSI.2020.3037295
IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords
DocType
Volume
Coarse-fine ADC,digital calibration,dynamic amplifier,pipelined-SAR ADC,split-ADC
Journal
68
Issue
ISSN
Citations 
2
1549-8328
1
PageRank 
References 
Authors
0.36
0
8
Name
Order
Citations
PageRank
Yuefeng Cao110.36
Shumin Zhang231.15
Tianli Zhang331.15
Yongzhen Chen434.82
Yutong Zhao512.05
Chixiao Chen664.36
Fan Ye76321.55
Junyan Ren815441.40