Name
Title | ||
|---|---|---|
Speed optimal FPGA implementation of the encryption algorithms for telecom applications |
Abstract | ||
|---|---|---|
The last two decades have seen a revolution in telecom technology with the evolution of three wireless mobile communication standards, namely, GPRS to 3G, 3G to 4G, and 4G to 5G. 5G offers faster download speeds and enables high connectivity between devices such as mobile phones, displays, smart homes, and smart cars because of its high reliability and high bandwidths (up to 10 Gbps). However, at the same time, data and personal information are also more susceptible to theft because of the high connectivity. Such threats can be addressed using electronic data encryption using the advanced encryption standard (AES). Because of their reconfigurable and parallel architectures, Field-Programmable Gate Arrays (FPGAs) are getting popular in VLSI design flows to enable the pre-silicon validation of designs faster data rates in real-time. FPGAs also serve as platforms for software development in the pre-silicon environment owing to their faster speeds. The design community is also heavily relying on High-Level Synthesis (HLS) tools in VLSI design flows. HLS platforms enable the new designs to improve the process with sustained authentication between two analytical selections from conventional functional specifications. We propose a high-throughput FPGA implementation based on high-level Synthesis for the AES algorithm. The implementation uses a 128-bit key and is highly suited for telecom applications such as 5G. Researchers have developed and tested the setup and then used the Vivado HLS tool to evaluate various HLS guidelines as per the implementation. The generated Verilog RTL was verified and implemented on Xilinx Kintex 7 and Virtex 6 FPGAs. Since using the same resources, we have seen significant results than existing methods achieved by individual investigators. We have also verified the design for functionality by checking the ciphertext output from our design against a reference design output for the same input plaintext. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1016/j.micpro.2020.103324 | Microprocessors and Microsystems |
Keywords | DocType | Volume |
Advanced encryption standard,Field programmable gate array,Register transfer level,Telecom,Xilinx high-level synthesis | Journal | 79 |
ISSN | Citations | PageRank |
0141-9331 | 1 | 0.37 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Prateek Sikka | 1 | 4 | 2.12 |
| Abhijit R. Asati | 2 | 13 | 5.70 |
| Chandra Shekhar | 3 | 94 | 13.69 |