Name
Abstract | ||
|---|---|---|
A rising tide of exploits, in the recent years, following a steady discovery of the many vulnerabilities pervasive in modern computing systems has led to a growing number of studies in designing systems-on-chip (SoCs) with security as a first-class consideration. Following the momentum behind RISC-V-based systems in the public domain, much of this effort targets RISC-V-based SoCs; most ideas, however, are independent of this choice. In this manuscript, we present a consolidation of our early efforts along these lines in designing a secure SoC around RISC-V, named ITUS. In particular, we discuss a set of primitive building blocks of a secure SoC and present some of the implemented security subsystems using these building blocks—such as secure boot, memory protection, PUF-based key management, a countermeasure methodology for RISC-V micro-architectural side-channel leakage, and an integration of the open keystone-enclaves for TEE. The current ITUS SoC prototype, integrating the discussed security subsystems, was built on top of the lowRISC project; however, these are portable to any other SoC code base. The SoC prototype has been evaluated on an FPGA. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1007/s41635-020-00108-8 | Journal of Hardware and Systems Security |
Keywords | DocType | Volume |
Secure SoC, Design-for-security, Threat modeling, RISC-V, Secure boot, Side-channel attack countermeasures, Memory protection, TEE, PUF | Journal | 4 |
Issue | ISSN | Citations |
4 | 2509-3428 | 0 |
PageRank | References | Authors |
0.34 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vinay B. Y. Kumar | 1 | 0 | 0.68 |
| Deb, Suman | 2 | 24 | 4.59 |
| Naina Gupta | 3 | 0 | 0.34 |
| Shivam Bhasin | 4 | 311 | 58.38 |
| Jawad Haj-Yahya | 5 | 5 | 1.75 |
| Anupam Chattopadhyay | 6 | 318 | 62.76 |
| Avi Mendelson | 7 | 517 | 55.88 |