Name
Title | ||
|---|---|---|
Fine Resolution Delay Tuning Method To Improve The Linearity Of An Unbalanced Time-To-Digital Converter On A Xilinx Fpga |
Abstract | ||
|---|---|---|
In this study, a method for fine adjustment of Xilinx field programmable gate array (FPGA) routing delays is proposed and applied to improve the linearity of an unbalanced multi-measurement time-to-digital converter (TDC). The delay control method increases load capacitances of interconnect points of switch matrices by small amounts using additional connections to unused interconnects in the FPGA fabric. The novel delay control method uses the tool command language (TCL) scripting feature available in the Xilinx Vivado tool to automatically add wires into a fully placed and routed design. A total of 61 additional wires were successfully and automatically added to reduce the differential and integral non-linearities of the target TDC from 0.51 and -0.54 LSB to 0.05 and 0.06 LSB, respectively (reduction factors of 10.2 and 9) for an LSB equal to 333 ps. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1049/iet-cds.2020.0026 | IET CIRCUITS DEVICES & SYSTEMS |
Keywords | DocType | Volume |
delays, field programmable gate arrays, time-digital conversion, integrated circuit interconnections, network routing, integrated circuit design, fine resolution delay, Xilinx FPGA, Xilinx field programmable gate array routing delays, multimeasurement time-to-digital converter, delay control method, interconnect points, Xilinx Vivado tool, fully placed routed design, LSB, multimeasurement TDC, time-to-digital converter, integral nonlinearities, differential nonlinearities, switch matrices | Journal | 14 |
Issue | ISSN | Citations |
8 | 1751-858X | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Safa Berrima | 1 | 5 | 0.92 |
| Yves Blaquière | 2 | 24 | 11.24 |
| Yvon Savaria | 3 | 566 | 139.13 |