Yves Blaquière - Citegraph

Author Info

Name	Affiliation	Papers
YVES BLAQUIÈRE	Univ Quebec, Dept Informat, Montreal, PQ H3C 3P8, Canada	28
Collaborators	Citations	PageRank
37	24	11.24
Referers	Referees	References
59	268	95

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100268

Publications (28 rows)

Collaborators (37 rows)

Referers (59 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Acceleration Of The Secure Hash Algorithm-256 (Sha-256) On An Fpga-Cpu Cluster Using Opencl	0	0.34	2021
A Versatile 200-V Capacitor-Coupled Level Shifter for Fully Floating Multi-MHz Gate Drivers	2	0.49	2021
Fine Resolution Delay Tuning Method To Improve The Linearity Of An Unbalanced Time-To-Digital Converter On A Xilinx Fpga	0	0.34	2020
A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration.	0	0.34	2019
Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits.	0	0.34	2018
A pattern-based routing algorithm for a novel electronic system prototyping platform.	0	0.34	2018
A Multi-Measurements Ro-Tdc Implemented In A Xilinx Field Programmable Gate Array	1	0.40	2017
Sub-ps resolution programmable delays implemented in a Xilinx FPGA	0	0.34	2017
A novel spatially configurable differential interface for an electronic system prototyping platform.	0	0.34	2016
A compact spatially configurable differential input stage for a field programmable interconnection network	0	0.34	2016
Towards an efficient SEU effects emulation on SRAM-based FPGAs.	0	0.34	2016
An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform.	1	0.36	2016
An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs	0	0.34	2015
Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis	2	0.40	2015
An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks	0	0.34	2015
Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit	3	0.45	2015
Circuit Level Modeling of Extra Combinational Delays in SRAM-Based FPGAs Due to Transient Ionizing Radiation	1	0.42	2015
Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain	5	0.58	2014
A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems	0	0.34	2014
Configurable Input–Output Power Pad for Wafer-Scale Microelectronic Systems	1	0.35	2013
SoC systems thermal monitoring using embedded sensor cells unit	0	0.34	2012
A large range and fine tuning configurable Bandgap reference dedicated to wafer-scale systems	0	0.34	2011
A spatially reconfigurable fast differential interface for a wafer scale configurable platform.	2	0.70	2010
Workflow For An Electronic Configurable Prototyping System	4	0.68	2009
Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL	0	0.34	2008
Digital signal propagation on a wafer-scale smart active programmable interconnect.	1	0.54	2008
Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os.	1	0.48	2007
VHDL design of a priority interrupt controller and synchronizer for the MC68008	0	0.34	1990