Name
Abstract | ||
|---|---|---|
The outsourcing of several untrusted intellectual property designs makes the development of integrated circuits vulnerable to piracy, overbuilding, reverse engineering, and hardware Trojan (HT). To thwart the hardware-based attacks, several design-for-trust (DFT) techniques are reported in the literature. In this paper, we analyze that the existing methods are inefficient to prevent hardware Trojan attacks and also exhibit significant design overhead. Hence, we propose a novel DFT technique that effectively increases the immunity of design against the Trojan attack while requiring minimal overhead. In the proposed technique, various new light-weight key-gate topologies are proposed that effectively increase the triggering probability of Trojan at the rare-triggered nets by encrypting the design. We also propose a new encryption algorithm that identifies an optimal node using a new metric called vulnerability factor in-order to replace it with the proposed key-gate. Our encryption algorithm significantly reduces the number of vulnerable-nets with minimum replacements. The simulation results show that the proposed key-gates reduce on an average 34.2 percent and 35.1 percent per-gate area and energy respectively over the stack-based key-gates. Finally, our DFT technique gives on an average 94 percent area overhead reduction as compared to the best known DFT technique on the ISCAS-85 benchmarks. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TETC.2018.2795706 | IEEE Transactions on Emerging Topics in Computing |
Keywords | DocType | Volume |
Design-for-trust,logic encryption,hardware Trojan,key-gates,rare-triggered nets | Journal | 8 |
Issue | ISSN | Citations |
3 | 2168-6750 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vijaypal Singh Rathor | 1 | 3 | 0.74 |
| Bharat Garg | 2 | 32 | 9.88 |
| Sharma, G.K. | 3 | 7 | 1.87 |