Name
Abstract | ||
|---|---|---|
Unaligned accesses are forbidden in many high-performance architectures. In most of these architectures, the least significant address bits of a multibyte memory access must be zero. Otherwise, the program generating the access is considered erroneous and an exception is flagged. The objective of this paper is to propose an alternative behaviour using the least significant address bits to encode the byte order of the accessed data. Modifying a traditional architecture to support the proposed behaviour presents several advantages, including backward compatibility at binary-code level, and the possibility of carrying out an endianness conversion during multibyte memory accesses without increasing the execution time nor using additional opcodes. The technique is demonstrated by modifying an OpenRISC 1000 implementation without introducing any penalty in hardware resources or performance. Subroutines written and compiled for the traditional architecture and originally designed for only the native byte order can, in the modified architecture, read and write data in a non-native byte order without any need to recompile. The execution of a sample algorithm operating on non-native byte order shows a reduction of 60% in the user execution time in the modified implementation when compared to the original implementation. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1016/j.micpro.2020.103268 | Microprocessors and Microsystems |
Keywords | DocType | Volume |
ISA,Data alignment,Byte order,Endianness,Shared memory,MPSoC | Journal | 78 |
ISSN | Citations | PageRank |
0141-9331 | 0 | 0.34 |
References | Authors | |
0 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Guerrero | 1 | 14 | 5.86 |
| German Cano-Quiveu | 2 | 0 | 0.34 |
| Jorge Juan-chico | 3 | 31 | 6.52 |
| Alejandro Millán | 4 | 10 | 5.77 |
| Manuel J. Bellido | 5 | 82 | 11.82 |
| J. Viejo | 6 | 3 | 2.65 |
| Paulino Ruiz-de-clavijo | 7 | 21 | 6.72 |
| Enrique Ostúa | 8 | 3 | 3.05 |