Name
Abstract | ||
|---|---|---|
Virtually all processors today employ a store buffer (SB) to hide store latency. However, when the store buffer is full, store latency is exposed to the processor causing pipeline stalls. The default strategies to mitigate these stalls are to issue prefetch for ownership requests when store instructions commit and to continuously increase the store buffer size. While these strategies considerably increase memory-level parallelism for stores, there are still applications that suffer deeply from stalls caused by the store buffer. Even worse, store-buffer induced stalls increase considerably when simultaneous multi-threading is enabled, as the store buffer is statically partitioned among the threads.In this paper, we propose a highly selective and very aggressive prefetching strategy to minimize store-buffer induced stalls. Our proposal, Store-Prefetch Burst (SPB), is based on the following insights: i) the majority of store-buffer induced stalls are caused by a few stores; ii) the access pattern of such stores are easily predictable; and iii) the latency of the stores is not commonly hidden by standard cache prefetchers, as hiding their latency would require tremendous prefetch aggressiveness. SPB accurately detects contiguous store-access patterns (requiring just 67 bits of storage) and prefetches the remaining memory blocks of the accessed page in a single burst request to the L1 controller. SPB matches the performance of a 1024-entry SB implementation on a 56-entry SB (i.e., Skylake architecture). For a 14-entry SB (e.g., running four logical cores), it achieves 95.0% of that ideal performance, on average, for SPEC CPU 2017. Additionally, a 20-entry store buffer that incorporates SPB achieves the average performance of a standard 56-entry store buffer. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/MICRO50266.2020.00054 | 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) |
Keywords | DocType | ISBN |
boosting Store buffer efficiency,store latency,store instructions,store buffer size,worse store-buffer induced stalls,highly selective prefetching strategy,very aggressive prefetching strategy,contiguous store-access patterns,20-entry store buffer,56-entry store buffer,store-prefetch bursts,word length 67.0 bit | Conference | 978-1-7281-7384-9 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Juan Manuel Cebrian | 1 | 24 | 10.19 |
| Stefanos Kaxiras | 2 | 1218 | 96.24 |
| Alberto Ros | 3 | 384 | 32.60 |