Title
A Fast Response Reference Voltage Buffer for 12b 200MS/s SAR ADC
Abstract
This paper analyzes the impact of decoupling capacitor to the power consumption of reference voltage buffer (RVB) and proposes a PMOS-assisted structure with bulk modulation that is applied to high speed ADCs. The response to reference overshoot is improved by PMOS source follower branch. The response enhanced techniques consist of a pair of cross-coupled capacitors and bulk modulation, further reducing the reference voltage settling time. The concept is proofed by applied to a 12b 200MS/s SAR ADC without redundancy in 28 nm CMOS. The ADC and RVB consume 3.63mW and 14.11mW, respectively. The simulation shows that the SNDR and SFDR are 65.39 dB and 77.25dB with a 92.2 MHz input.
Year
DOI
Venue
2020
10.1109/MWSCAS48704.2020.9184609
2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)
Keywords
DocType
ISSN
SAR ADC,reference driver,split-switching method,source follower
Conference
1548-3746
ISBN
Citations 
PageRank 
978-1-7281-8059-5
0
0.34
References 
Authors
0
3
Name
Order
Citations
PageRank
Wenbin He1135.19
Fan Ye26321.55
Junyan Ren315441.40