Name
Abstract | ||
|---|---|---|
Common physical attacks in integrated circuits make use of microprobes to sense information in specific bus lines. It can be mitigated with additional built-in circuitry to detect deviations in the expected capacitance of the bus lines caused by these attacking probes. The strategy is to convert capacitance deviations into delay deviations, followed by time-to-digital conversion to provide a signature that is used to identify a probe attack. However, the sensitivity to delay deviation is highly related to individual sizes of elements that compose the protecting circuit. In this paper, a multi-objective optimization-based methodology is applied to optimize the required silicon area as well as the robustness and parametric manufacturing yield of a microprobe detector. We present the required computational modeling of the circuit optimization objectives and constraints for a successful application of optimization methods. Results show that this approach reduces the required circuit gate area up to 50% compared to manual sizing, while guaranteeing high manufacturing yield. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/SBCCI50935.2020.9189932 | 2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI) |
Keywords | DocType | ISBN |
Security,Microprobing,Invasive Attacks,Optimization,MOPSO | Conference | 978-1-7281-9626-8 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alessandro Girardi | 1 | 0 | 0.34 |
| Helmut E. Graeb | 2 | 269 | 36.22 |