Name
Title | ||
|---|---|---|
SuSy: a programming model for productive construction of high-performance systolic arrays on FPGAs |
Abstract | ||
|---|---|---|
ABSTRACTSystolic algorithms are one of the killer applications on spatial architectures such as FPGAs and CGRAs. However, it requires a tremendous amount of human effort to design and implement a high-performance systolic array for a given algorithm using the traditional RTL-based methodology. On the other hand, existing high-level synthesis (HLS) tools either (1) force the programmers to do "micro-coding" where too many optimizations must be carried out through tedious code restructuring and insertion of vendor-specific pragmas, or (2) give them too little control to influence a push-button compilation flow to achieve high quality of results. To tackle these challenges, we introduce SuSy, a programming framework composed of a domain-specific language (DSL) and a compilation flow that enables programmers to productively build high-performance systolic arrays on FPGAs. With SuSy, programmers express the design functionality in the form of uniform recurrence equations (UREs), which can describe algorithms from a wide spectrum of applications as long as the underlying computation has a uniform dependence structure. The URE description in SuSy is followed by a set of decoupled spatial mapping primitives that specify how to map the equations to a spatial architecture. More concretely, programmers can apply space-time transformations and several other memory and I/O optimizations to build a highly efficient systolic architecture productively. Experimental results show that SuSy can describe various algorithms with UREs and generate high-performance systolic arrays by spatial optimizations. For instance, the SGEMM benchmark written in SuSy can approach the performance of the manual design optimized by experts, while using 30× fewer lines of code. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1145/3400302.3415644 | International Conference on Computer-Aided Design |
Keywords | DocType | ISSN |
DSL,FPGA,Systolic Array,Space-Time Transformation,URE | Conference | 1933-7760 |
Citations | PageRank | References |
1 | 0.36 | 24 |
Authors | ||
16 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yi-Hsiang Lai | 1 | 35 | 4.95 |
| Hongbo Rong | 2 | 1 | 1.04 |
| Size Zheng | 3 | 16 | 1.62 |
| Weihao Zhang | 4 | 1 | 0.36 |
| Xiuping Cui | 5 | 1 | 0.70 |
| Yunshan Jia | 6 | 1 | 0.36 |
| J. Wang | 7 | 1436 | 105.75 |
| Brendan Sullivan | 8 | 1 | 0.36 |
| Zhiru Zhang | 9 | 1020 | 71.74 |
| Yun Liang | 10 | 868 | 59.55 |
| Youhui Zhang | 11 | 202 | 28.36 |
| Jason Cong | 12 | 7069 | 515.06 |
| Nithin George | 13 | 1 | 0.36 |
| Jose Alvarez | 14 | 1 | 0.36 |
| Christopher J. Hughes | 15 | 988 | 63.34 |
| Pradeep K. Dubey | 16 | 3432 | 292.69 |