Name
Title | ||
|---|---|---|
Epitaxial Gd<inf>2O</inf><inf>3</inf>on Si (111) Substrate by Sputtering to Enable Low Cost SOI |
Abstract | ||
|---|---|---|
Silicon on insulator (SOI) enables RF technology at advanced nodes [1]. The SOI-wafer cost is the key challenge due to complex manufacturing processes such as “smart cut” or wafer bonding [2]. The epitaxial growth of rare earth (RE) oxides followed by epi-Si growth is extensively explored for SOI stack preparation. Low lattice mismatch (~0.5%) between Si and RE oxides such as Ce
<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>
O
<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>
, Pr
<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>
0
<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>
, Gd
<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>
0
<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>
etc. [3], make it suitable for isolation oxide (IO) for SOI. Among all, Gd
<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>
0
<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>
is proven most promising, due to stable oxidation state (+3) [3], large band gap (~5.9 eV) and, sufficient band offset
<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\Delta \mathrm{E}_{\mathrm{c}}=2.1\mathrm{eV}\&\Delta \mathrm{E}_{\mathrm{v}}=2.8\mathrm{eV})$</tex>
[4]. Epi-Gd
<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>
0
<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>
has potential to be an attractive alternative for gate dielectric and IO layer [5]–[8] in advanced CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/DRC.2018.8442170 | 2018 76th Device Research Conference (DRC) |
DocType | ISSN | ISBN |
Conference | 1548-3770 | 978-1-5386-3029-7 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| K. R. Khiangte Amlta | 1 | 0 | 0.34 |
| Apurba Laha | 2 | 0 | 1.01 |
| Mahapatra, S. | 3 | 22 | 4.83 |
| U. Gangway | 4 | 0 | 0.34 |