Name
Abstract | ||
|---|---|---|
TVM is a AI compiler supports both graph-level and operator-level optimization on machine learning models. It provides an optimizable flow to deploy on diverse target devices. By exploiting TVM schedule, we can optimize the codegen behavior for our RISC-V architecture. Since RISCV is configurable with the selection on different extension, we can enable multiple extensions depends on the application scene. In our work, we present the flow for enabling and optimizing the RISC-V P extension toward QNN models from TVM. With support from LLVM and a customized deep learning runtime (DLR), we verified our work on both FLOAT32 and prequantized models from Tensorflow Lite. Experiments shows that comparing with FLOAT32 models, our work can achieve 2.7-7.0 times of performance improvement with regard to total instruction count at runtime for pre-quantized version with a set of benchmarks including Mobilenet and Inception-v3. As for accuracy issue, the degradation is tiny for quantization version among 500 images. All experiments are running on RISC-V simulator, Spike with P extension support. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/VLSI-DAT49148.2020.9196477 | 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) |
Keywords | DocType | ISSN |
Inception-v3,Mobilenet,Tensorflow Lite,deep learning runtime,LLVM,RISC-V P extension,graph-level optimization,FLOAT32 models,QNN models,codegen behavior,TVM schedule,machine learning,operator-level optimization,AI compiler,RISC-V architecture,RISC-V simulator | Conference | 2380-7369 |
ISBN | Citations | PageRank |
978-1-7281-6084-9 | 0 | 0.34 |
References | Authors | |
3 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yi-Ru Chen | 1 | 0 | 0.34 |
| Hui-Hsin Liao | 2 | 0 | 0.68 |
| Chia-Hsuan Chang | 3 | 0 | 0.68 |
| Che-Chia Lin | 4 | 0 | 0.68 |
| Chao-Lin Lee | 5 | 1 | 3.41 |
| Yuan-Ming Chang | 6 | 3 | 1.88 |
| Chun-Chieh Yang | 7 | 5 | 2.62 |
| Jenq Kuen Lee | 8 | 459 | 48.71 |