| Support Convolution of CNN with Compression Sparse Matrix Multiplication Flow in TVM | 0 | 0.34 | 2021 |
| Accelerate Binarized Neural Networks with Processing-in-Memory Enabled by RISC-V Custom Instructions | 0 | 0.34 | 2021 |
| Accelerating NNEF Framework on OpenCL Devices Using clDNN | 0 | 0.34 | 2020 |
| Experiments and optimizations for TVM on RISC-V Architectures with P Extension | 0 | 0.34 | 2020 |
| Enabling Android NNAPI Flow for TVM Runtime. | 0 | 0.34 | 2020 |
| Devise Sparse Compression Schedulers to Enhance FastText Methods. | 0 | 0.34 | 2020 |
| Sparse-Matrix Compression Primitives with OpenCL Framework to Support Halide | 0 | 0.34 | 2019 |
| Support OpenCL 2.0 Compiler on LLVM for PTX Simulators | 1 | 0.41 | 2019 |
| Architecture and Compiler Support for GPUs Using Energy-Efficient Affine Register Files. | 2 | 0.46 | 2018 |
| Viennacl Plus Plus : Enable Tensorflow/Eigen Via Viennacl With Opencl C Plus Plus Flow | 0 | 0.34 | 2018 |
| A Probabilistic Framework for Compiler Optimization with Multithread Power-Gating Controls | 0 | 0.34 | 2016 |
| Energy Efficient Affine Register File for GPU Microarchitecture | 2 | 0.45 | 2016 |
| OpenCV Optimization on Heterogeneous Multi-core Systems for Gesture Recognition Applications | 0 | 0.34 | 2016 |
| Vector data flow analysis for SIMD optimizations on OpenCL programs | 1 | 0.39 | 2016 |
| The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems | 1 | 0.36 | 2015 |
| Guest Editorial: Embedded Multicore Systems and Applications | 1 | 0.36 | 2015 |
| Register spilling via transformed interference equations for PAC DSP architecture | 0 | 0.34 | 2014 |
| Optimized memory access support for data layout conversion on heterogeneous multi-core systems | 0 | 0.34 | 2014 |
| Achieving spilling-friendly register file assignment for highly distributed register files | 0 | 0.34 | 2014 |
| The design of LLVM-based shader compiler for embedded architecture | 0 | 0.34 | 2014 |
| Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs | 4 | 0.39 | 2014 |
| Compilers for Low Power with Design Patterns on Embedded Multicore Systems | 2 | 0.37 | 2013 |
| Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files. | 1 | 0.35 | 2012 |
| Enabling an OpenCL Compiler for Embedded Multicore DSP Systems | 6 | 0.53 | 2012 |
| Case study: stereo vision experiments with multi-core software API on embedded MPSoC environments | 0 | 0.34 | 2012 |
| Compiler supports for VLIW DSP processors with SIMD intrinsics | 4 | 0.48 | 2012 |
| Parallelization of Belief Propagation on Cell Processors for Stereo Vision | 3 | 0.45 | 2012 |
| C++ Compiler Supports for Embedded Multicore DSP Systems | 0 | 0.34 | 2011 |
| Parallelization of a Bokeh application on embedded multicore DSP systems. | 0 | 0.34 | 2011 |
| Support of software framework for embedded multi-core systems with Android environments | 3 | 0.58 | 2011 |
| A multi-core software API for embedded MPSoC environments | 1 | 0.36 | 2010 |
| Programming Model And Tools For Embedded Multicore Systems | 0 | 0.34 | 2010 |
| pTest: An adaptive testing tool for concurrent software on embedded multicore processors | 1 | 0.40 | 2009 |
| Support of Paged Register Files for Improving Context Switching on Embedded Processors | 0 | 0.34 | 2009 |
| Configurable SID-based multi-core simulators for embedded system education | 2 | 0.56 | 2009 |
| Enabling Streaming Remoting on Embedded Dual-Core Processors | 12 | 0.98 | 2008 |
| Parallelization of belief propagation method on embedded multicore processors for stereo vision | 5 | 0.46 | 2008 |
| Compilation for compact power-gating controls | 12 | 0.58 | 2007 |
| Enabling compiler flow for embedded VLIW DSP processors with distributed register files | 7 | 0.54 | 2007 |
| Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains | 3 | 0.38 | 2007 |
| PAC DSP Core and Application Processors. | 21 | 1.67 | 2006 |
| Compilers for leakage power reduction | 37 | 1.29 | 2006 |
| Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors | 5 | 0.60 | 2006 |
| System-level design space exploration for security processor prototyping in analytical approaches | 1 | 0.42 | 2005 |
| A sink-n-hoist framework for leakage power reduction | 9 | 0.77 | 2005 |
| Interprocedural probabilistic pointer analysis | 13 | 0.69 | 2004 |
| Efficient support of java RMI over heterogeneous wireless networks | 5 | 0.48 | 2004 |
| Support and optimization for parallel sparse programs with array intrinsics of Fortran 90 | 2 | 0.37 | 2004 |
| Case study: an infrastructure for C/ATLAS environments with object-oriented design and XML representation | 1 | 0.41 | 2004 |
| Specification and architecture supports for component adaptations on distributed environments | 3 | 0.41 | 2004 |
