Name
Abstract | ||
|---|---|---|
Spin-Transfer Torque Random Access Memory (STT-RAM) is a potential alternative for SRAM-based on-chip caches. STT-RAM offers high density and low leakage power, thereby can be used to build a large capacity last-level caches (LLC). Unfortunately, the write latency of the STT-RAM is significantly longer, and its write energy is considerably higher compared to SRAM. To mitigate these concerns, researchers have proposed hybrid caches that are comprised of SRAM and STT-RAM regions. In such hybrid caches, an intelligent block placement policy is necessary to store as many write-intensive blocks in the SRAM region. This paper proposes an adaptive block placement framework with metadata embedding (ADAM) for hybrid caches. ADAM embeds metadata (i.e., write-intensity) into a cache block when it is evicted from LLC. When a cache block is brought from the main memory, metadata embedded in the block is extracted and used to determine the write-intensity of the block. Our evaluation shows that ADAM can improve performance by 26 % (on average) over a baseline block placement scheme. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ICCD50377.2020.00077 | 2020 IEEE 38th International Conference on Computer Design (ICCD) |
Keywords | DocType | ISSN |
Last-level Cache,Hybrid Cache,Non-Volatile Memory,STT-RAM | Conference | 1063-6404 |
ISBN | Citations | PageRank |
978-1-7281-9711-1 | 0 | 0.34 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Beomjun Kim | 1 | 0 | 0.34 |
| Prashant J. Nair | 2 | 346 | 15.74 |
| Seokin Hong | 3 | 59 | 8.42 |