Name
Abstract | ||
|---|---|---|
Non- Volatile Memory (NVM) systems require logging to support crash consistency. However, log operations introduce severe performance overhead. Recently, LAD was proposed to eliminate log operations for some transactions in which the total amount of updated cachelines is smaller than the Asynchronous DRAM Refresh (ADR) buffer, without affecting crash consistency. Nevertheless, on multicore, concurrent transactions tend to exhaust the ADR resource and hence log operations have to be conducted in LAD. In this study, we observe that a significant number of log operations could be avoided if each transaction run alone. To eliminate these unnecessary log operations, this paper proposes virtual ADR buffers to decouple buffering from the ADR's reliable writing data. Specifically, only logless operations are allowed to access ADR resources. Additionally, this paper proposes to adopt redo log with DRAM cache to speed up the transaction commit speed. The evaluation results demonstrate that our proposed scheme can efficiently reduce log operation up to 94.9 % and improve the transaction throughput up to 78.6 %. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ICCD50377.2020.00099 | 2020 IEEE 38th International Conference on Computer Design (ICCD) |
Keywords | DocType | ISSN |
Non-Volatile Memory,Crash Consistency,Memory Hierarchy,Computer Architecture | Conference | 1063-6404 |
ISBN | Citations | PageRank |
978-1-7281-9711-1 | 0 | 0.34 |
References | Authors | |
11 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhiyuan Lu | 1 | 2 | 1.40 |
| Jianhui Yue | 2 | 148 | 9.53 |
| Yifu Deng | 3 | 2 | 1.40 |
| Yifeng Zhu | 4 | 513 | 35.33 |