Title
Hierarchical Analog Power-Down Synthesis
Abstract
Analog circuits can be switched into power-down mode to reduce their overall power consumption. State-of-the-art synthesis tools can automatically construct the power-down circuitry of such a circuit block. However, when connecting such sub-circuit blocks with each other, the correct functionality of the resulting power-down circuitry cannot be guaranteed anymore. This paper presents a new power-down synthesis method for hierarchical analog circuits. The synthesis problem is partitioned into smaller sub-problems for each individual sub-circuit block and intermediate results are reused. The proposed method is demonstrated for a high input impedance differential amplifier.
Year
DOI
Venue
2020
10.1109/ICECS49266.2020.9294889
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Keywords
DocType
ISBN
power-saving modes,analog power-down synthesis,hierarchical circuits,constraint programming
Conference
978-1-7281-6045-0
Citations 
PageRank 
References 
0
0.34
4
Authors
2
Name
Order
Citations
PageRank
Maximilian Neuner100.34
Helmut E. Graeb226936.22