Name
Abstract | ||
|---|---|---|
As FPGA-based accelerators become ubiquitous and more powerful, the demand for integration with High-Performance Memory (HPM) grows. Although HPMs offer a much greater bandwidth than standard DDR4 DRAM, they introduce new design challenges such as increased latency and higher bandwidth mismatch between memory and FPGA cores. This paper presents a scalable architecture for convolutional neural network accelerators conceived specifically to address these challenges and make full use of the memory's high bandwidth. The accelerator, which was designed using high-level synthesis, is highly configurable. The intrinsic parallelism of its architecture allows near-perfect scaling up to saturating the available memory bandwidth. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/HPEC43674.2020.9286162 | 2020 IEEE High Performance Extreme Computing Conference (HPEC) |
Keywords | DocType | ISSN |
scalable architecture,CNN accelerators leveraging High-Performance memories,FPGA-based accelerators,High-Performance Memory,greater bandwidth,standard DDR4 DRAM,design challenges,higher bandwidth mismatch,FPGA cores,convolutional neural network accelerators,high-level synthesis,available memory bandwidth | Conference | 2377-6943 |
ISBN | Citations | PageRank |
978-1-7281-9220-8 | 0 | 0.34 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Maarten Hattink | 1 | 0 | 0.34 |
| Giuseppe Di Guglielmo | 2 | 107 | 15.57 |
| Luca P. Carloni | 3 | 1713 | 120.17 |
| Keren Bergman | 4 | 669 | 64.58 |