Name
Abstract | ||
|---|---|---|
A nonvolatile FPGA, where the circuit-configuration information still remains without power supply, offers a powerful solution against the standby power issue. In this paper, a synthesizable nonvolatile FPGA is proposed, where the circuit-configuration information is described in a hardware description language and is pushed through a standard ASIC tool flow with nonvolatile logic circuit IPs such as nonvolatile flip-flops. The use of the ASIC tool flow makes it possible to migrate any arbitrary process technology and to perform architecture-level simulation with physical information. As a typical design example under 55nm CMOS/100nm magnetic tunnel junction (MTJ) technologies, the performance of the proposed nonvolatile FPGA is evaluated in comparison with that of a CMOS-only volatile FPGA. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ISMVL49045.2020.000-6 | 2020 IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL) |
Keywords | DocType | ISSN |
FPGA,Nonvolatile logic,logic synthesis,hardware description language,standard-cell-based design | Conference | 0195-623X |
ISBN | Citations | PageRank |
978-1-7281-5407-7 | 0 | 0.34 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daisuke Suzuki | 1 | 47 | 7.32 |
| Takahiro Hanyu | 2 | 441 | 78.58 |