Name
Abstract | ||
|---|---|---|
This brief revises the recent design trends of linear low-dropout regulators. The design issues and advantages of analog LDOs (ALDO) are discussed. High-performance operation and high rejection to supply noise when delivering large current values is a major advantage of the ALDO, but transient response when transitioning from standby operation to full load is a major issue; the main limitation is the slow charging/discharging of the large gate's capacitor of the pass transistor. This issue is more critical when designing full-on chip ALDOs, where large load capacitors are not available. Digital LDOs (DLDO) employ digital controllers that drive the segmented pass transistor, in most of the cases operate in triode region. The digital nature of the DLDO scales with the technology, but its rejection to supply noise is limited. Mixed-mode LDOs take advantage of the properties of both ALDO and DLDOs. Transient is managed by the agile DLDO and steady state operation is mainly handled by the clock glitch free ALDO. In this brief, all three architectures are revisited. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/TCSII.2020.3046410 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | DocType | Volume |
Linear regulator,linear low-dropout regulators,LDO,digital regulator,mixed-mode linear regulator,LDO ALDO,power management,on-chip regulators | Journal | 68 |
Issue | ISSN | Citations |
2 | 1549-7747 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jose Silva-Martinez | 1 | 630 | 86.56 |
| Xiaosen Liu | 2 | 92 | 12.86 |
| Dadian Zhou | 3 | 25 | 3.02 |