Paper Info
Title
Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction
Abstract
Power supply noise induces extra timing delay or even malfunctions in modern power-demanding VLSI chips. Traditional reactive noise mitigation is often too late to suppress emergent supply noise due to the long latency of voltage boosting. This paper proposes a proactive method for mitigating emergent supply noises and avoiding unexpected failures in power-hungry VLSI designs with two contributions. First, a major-minor voltage regulator (MMVR) structure, which enables quick and widerange voltage scaling with small ripples, is proposed. Second, a lightweight current predictor consisting of a six-layer decision tree regressor achieves over 0.98 correlation for 50-cycle-ahead prediction in 25 RISC-V benchmark programs. Experimental results with a multi-core RISC-V design show that the proposed method mitigates the supply noise within 30 mV while the noise exceeds 70 mV with the conventional reactive mitigation. Also, the average supply voltage is compensated during the power-demanding operation.
Year
DOI
Venue
2020
10.1109/ITC44778.2020.9325257
2020 IEEE International Test Conference (ITC)
Keywords
DocType
ISSN
timing delay,voltage boosting,power-hungry VLSI designs,lightweight current predictor,proactive supply noise mitigation,low-latency minor voltage regulator,lightweight current prediction,power supply noise,power-demanding VLSI chips,reactive noise mitigation,major-minor voltage regulator structure,MMVR structure,widerange voltage scaling,quick voltage scaling,decision tree regressor,RISC-V benchmark programs,multicore RISC-V design,power-demanding operation,voltage 30.0 mV
Conference
1089-3539
ISBN
Citations 
PageRank 
978-1-7281-9114-0
0
0.34
References 
Authors
0
2
Name
Order
Citations
PageRank
Jun Chen118727.66
Masanori Hashimoto246279.39