Name
Abstract | ||
|---|---|---|
There is a growing number of integrated circuits that deploy hybrid test schemes combining on-chip test compression with logic BIST, with both techniques working synergistically to deliver high quality tests. As their architectural differences are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This paper presents maXpress – an X-tolerant programmable compactor deploying a new scan chain selection mechanism capable of completely (as required by many in-system test applications) masking X states within redefinable groups of scan chains and designated scan shift cycles. In addition to the new architecture, the paper proposes an algorithm to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for a variety of industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ITC44778.2020.9325266 | 2020 IEEE International Test Conference (ITC) |
Keywords | DocType | ISSN |
built-in self-test,embedded-test,scan-based testing,test application time,unknown states,X-masking | Conference | 1089-3539 |
ISBN | Citations | PageRank |
978-1-7281-9114-0 | 1 | 0.35 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yingdi Liu | 1 | 8 | 2.51 |
| Sylwester Milewski | 2 | 3 | 3.12 |
| Grzegorz Mrugalski | 3 | 501 | 35.90 |
| Nilanjan Mukherjee | 4 | 1 | 0.35 |
| Janusz Rajski | 5 | 2460 | 201.28 |
| Jerzy Tyszer | 6 | 838 | 74.98 |
| Bartosz Wldarczak | 7 | 1 | 0.35 |