Title
Scalable yet rigorous floating-point error analysis
Abstract
ABSTRACTAutomated techniques for rigorous floating-point round-off error analysis are a prerequisite to placing important activities in HPC such as precision allocation, verification, and code optimization on a formal footing. Yet existing techniques cannot provide tight bounds for expressions beyond a few dozen operators---barely enough for HPC. In this work, we offer an approach embedded in a new tool called Satire that scales error analysis by four orders of magnitude compared to today's best-of-class tools. We explain how three key ideas underlying Satire helps it attain such scale: path strength reduction, bound optimization, and abstraction. Satire provides tight bounds and rigorous guarantees on significantly larger expressions with well over a hundred thousand operators, covering important examples including FFT, matrix multiplication, and PDE stencils.
Year
DOI
Venue
2020
10.5555/3433701.3433768
The International Conference for High Performance Computing, Networking, Storage, and Analysis
DocType
Citations 
PageRank 
Conference
0
0.34
References 
Authors
0
5
Name
Order
Citations
PageRank
Arnab Das111.37
Ian Briggs2264.56
Ganesh Gopalakrishnan31619130.11
Sriram Krishnamoorthy4120286.68
Pavel Panchekha532.73