Name
Abstract | ||
|---|---|---|
In this work, the implementations of the LBlock, Piccolo, Twine, and Klein lightweight ciphers in FPGA technology are studied in terms of area, frequency, throughput, and throughput/area. To accomplish this, loop unrolling and pipelining were employed in two phases. In the first phase, different loop unrolling factors were used to implement the round function of each cipher, while in the second phase, 2-stage pipelining with loop unrolling per stage was applied. The produced designs were implemented in Xilinx (Kintex-7) FPGA technology. Based on the implementation results, a detailed study on the above-mentioned design metrics was performed and important outcomes were derived. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/VLSI-SOC46417.2020.9344108 | 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC) |
Keywords | DocType | ISSN |
Lightweight ciphers,FPGA,loop unrolling,pipeline,area,frequency,throughput | Conference | 2324-8432 |
ISBN | Citations | PageRank |
978-1-7281-5410-7 | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. Moraitis | 1 | 0 | 0.34 |
| D. Seitanidis | 2 | 0 | 0.34 |
| George Theodoridis | 3 | 0 | 0.34 |
| O. Koufopavlou | 4 | 256 | 28.43 |