Name
Title | ||
|---|---|---|
10.5 A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET |
Abstract | ||
|---|---|---|
Recently, pipelined ADCs are frequently adopted as sub-ADCs in multi-channel timeinterleaved ADCs because a pipelined manner can reduce the number of interleaved channels by maximizing single-channel ADC operating speed. To reduce power consumption of residue amplifier, previous works [2], [4], [5] have explored power efficient residue amplifier architecture, such as dynamic amplifiers (DAs), open-loop amplifiers (OAs) and ring amplifiers (RAs). However, inter-stage gain error of power-efficient DAs, OAs, and RAs needs power-consuming gain calibration to compensate process, power supply, and temperature (PVT) variations. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISSCC42613.2021.9366051 | 2021 IEEE International Solid- State Circuits Conference (ISSCC) |
Keywords | DocType | Volume |
sub-ADCs,multichannel timeinterleaved ADCs,interleaved channels,single-channel ADC operating speed,power consumption,power efficient residue amplifier architecture,ring amplifiers,inter-stage gain error,power-efficient DAs,power-consuming gain calibration,power supply,pipelined SAR,2x-interleaved incremental delta-sigma ADC,source-follower-based residue-transfer scheme,pipelined ADCs,dynamic amplifiers,open-loop amplifiers,process, power supply, and temperature variation compensation,PVT variations,FinFET,size 7.0 nm,word length 12 bit | Conference | 64 |
ISSN | ISBN | Citations |
0193-6530 | 978-1-7281-9550-6 | 1 |
PageRank | References | Authors |
0.41 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seung-Yeob Baek | 1 | 4 | 1.51 |
| Il-Hoon Jang | 2 | 12 | 2.17 |
| Michael Choi | 3 | 11 | 2.32 |
| Hyungdong Roh | 4 | 1 | 0.41 |
| Woongtaek Lim | 5 | 1 | 0.41 |
| Youngjae Cho | 6 | 1 | 1.42 |
| jongshin shin | 7 | 7 | 4.33 |