jongshin shin - Citegraph

Author Info

Name	Affiliation	Papers
JONGSHIN SHIN	Samsung Elect, Yongin, South Korea	12
Collaborators	Citations	PageRank
89	7	4.33
Referers	Referees	References
31	41	11

Publications (12 rows)

Collaborators (89 rows)

Referers (31 rows)

Referees (41 rows)

Title	Citations	PageRank	Year
A Distributed Digital Ldo With Time-Multiplexing Calibration Loop Achieving 40a/Mm(2) Current Density And 1ma-To-6.4a Ultra-Wide Load Range In 5nm Finfet Cmos	0	0.34	2021
Samsung Physically Unclonable Function (SAMPUF™) and its integration with Samsung Security System	0	0.34	2021
10.5 A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET	1	0.41	2021
22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique.	0	0.34	2020
6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier	0	0.34	2020
An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss	0	0.34	2020
11.8 A 96.8%-Efficiency Continuous Input/Output-Current Step-Up/Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries	0	0.34	2020
A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS	3	0.39	2020
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme	0	0.34	2019
Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface	0	0.34	2018
A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization	2	0.39	2016
A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance	1	0.43	2013

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