Paper Info
Title
A Distributed Digital Ldo With Time-Multiplexing Calibration Loop Achieving 40a/Mm(2) Current Density And 1ma-To-6.4a Ultra-Wide Load Range In 5nm Finfet Cmos
Abstract
Although the number of cores is increasing continuously in modern microprocessors for applications such as HPC and AI, the available power is strictly limited by the thermal power budget. To overcome this limitation, recently, each core has been implemented with a dedicated integrated voltage regulator to increase the efficiency of power usage. Distributed digital LDO (DLDO) is a powerful solution for the integrated voltage regulator because it can supply uniform power over the entire core with reduced IR drop and help the thermal management [1– 4]. In the previous distributed DLDOs [1– 3], even though all LDO outputs are connected to drive the power-delivery network, the LDOs operate independently using their own controller, which occupies a large portion of the LDO size. Therefore, the current density in these types of structures is low. In [4], the distributed DLDO uses a dual-loop structure. In this scheme, the high current density can be achieved because the four shared global controllers control the 16 local LDOs (LLDOs) for highly accurate regulation. However, the LLDOs consume large quiescent current since they operate at a switching frequency of several-GHz for a fast transient response. Besides, the load current range is narrow due to the small switching duty-cycle range of the power FETs. Because of these drawbacks, the structure proposed in [4] has limitations in practical applications.
Year
DOI
Venue
2021
10.1109/ISSCC42613.2021.9365964
2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC)
DocType
Volume
ISSN
Conference
64
0193-6530
Citations 
PageRank 
References 
0
0.34
0
Authors
8
Name
Order
Citations
PageRank
dong hoon jung100.68
Tae-Hwang Kong2397.11
Jun Hyeok Yang301.01
Sang-Ho Kim411617.83
Kwang-Ho Kim5262.62
Jeongpyo Park600.34
Michael Choi7499.96
jongshin shin874.33