Paper Info
Title
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm
Abstract
This article presents a fully dynamic ringamp-based pipelined ADC with integrated reference buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of 14 fJ/conversion-step across this range. A “split-reference” regulation technique is introduced, which provides multiple buffered replicas with varying accuracies and output impedances to the core ADC circuitry, relaxing overall buffer design requirements and improving efficiency. The regulator blocks are implemented with fully dynamic discrete-time loops. Furthermore, a technique for background reconstruction of residue amplifier settling behavior is also described. The “scope-on-chip” captures high-resolution transient waveforms using a 1-bit stochastic ADC. It is shown how these waveform data can be used for optimization of ringamp biasing and PVT tracking. The ADC is fabricated in a 16-nm CMOS technology and at 1 GS/s with a Nyquist input achieves 59.5-dB SNDR, 75.9-dB SFDR, and 10.9-mW total power consumption with only 8% consumed by the reference regulation.
Year
DOI
Venue
2021
10.1109/JSSC.2020.3044831
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
A/D,ADC,asynchronous,dynamic,event driven,fully dynamic,high speed,low power,pipeline,pipelined ADC,reference buffer,reference regulation,ring amplifier,ring amplification,ringamp,scope on chip,stochastic ADC,voltage reference,voltage regulation,waveform capture
Journal
56
Issue
ISSN
Citations 
4
0018-9200
2
PageRank 
References 
Authors
0.37
0
6
Name
Order
Citations
PageRank
Benjamin P. Hershberg118023.21
Nereo Markulic2529.29
Jorge Lagos3185.57
Ewout Martens47517.77
Davide Dermit583.91
Jan Craninckx620.37