Paper Info
Title
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion
Abstract
A 4× interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a “passive-hold” mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude.
Year
DOI
Venue
2021
10.1109/JSSC.2021.3053893
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
A/D,ADC,asynchronous,direct-RF,dynamic,event driven,high speed,low power,passive-hold MDAC,pipeline,ring amplification,ring amplifier,ringamp,sample and hold,SHA,stochastic ADC
Journal
56
Issue
ISSN
Citations 
8
0018-9200
2
PageRank 
References 
Authors
0.39
0
7
Name
Order
Citations
PageRank
Benjamin P. Hershberg118023.21
Davide Dermit283.91
Barend van Liempd37411.81
Ewout Martens47517.77
Nereo Markulic5529.29
Jorge Lagos6185.57
Jan Craninckx720.39