Name
Abstract | ||
|---|---|---|
We report the highest sampling-rate single-chip ADC in any semiconductor technology. The circuit uses a 2x time-interleaved architecture integrating two track-and-hold amplifiers, each driving a 5-bit flash sub-ADC sampled at 64 GHz in antiphase. The digital outputs of the two sub-ADCs feed an on-die 128-GS/s thermometer-coded DAC whose sole purpose is for testing the ADC. The performance of the ADC-DAC combo, including the SFDR, and the ENOB of 4.1 bits up to 32-GHz input signals, was characterized on die and includes the impact of the DAC. The power consumption and layout footprint of the ADC, critical for operation at 128-GS/s, were minimized by employing novel 1-mA Cherry-Hooper comparators and quasi-CML MOS-HBT latches with active peaking, which reduced the footprint of each of the 64 ADC-lanes to 10μm 70μm. The total power consumption of the ADC is 1.25 W and the total die area of the ADC-DAC chip is 1.1mm×1.9mm. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/BCICTS.2018.8550990 | 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) |
Keywords | DocType | ISBN |
Flash ADC,Time-Interleaved,SiGe BiCMOS | Conference | 978-1-5386-6503-9 |
Citations | PageRank | References |
1 | 0.48 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alireza Zandieh | 1 | 2 | 0.86 |
| Peter Schvan | 2 | 1 | 0.48 |
| Sorin P. Voinigescu | 3 | 221 | 53.57 |