Name
Abstract | ||
|---|---|---|
This paper presents a synthesizable lead-lag quantization technique for all-digital delta sigma (ΔΣ) analog-to-digital converters (ADCs) based on voltage-controlled oscillator (VCO). Synthesizable circuitry is proposed to realize this technique, including a lead-lag phase detector (LLPD) and a tri-level resistor digital-to-analog converter (TRDAC) for feedback. It distinguishes the leading and lagging phases in an N-stage dual-VCO quantizer so that the resolution increases from log2(N+1) bits to log2(2 N + 1) bits. The TRDAC is also used as biasing DAC and suppresses the process variation. Taking the digital-like analog/mixed-signal design flow, the proposed ADC is implemented in 28-nm CMOS technology occupying only 0.0039 mm2. The simulation results show that it consumes 0.552 mW at a 0.9-V power supply, and achieves a 66.9-dB signal-to-noise-and-distortion ratio (SNDR) at 900 MS/s over 6-MHz bandwidth. With a similar SNDR to prior works, this technique lowers the Figure-of-Merit (FoM) to 25.5 fJ/conv.-step. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1016/j.mejo.2021.105007 | Microelectronics Journal |
Keywords | DocType | Volume |
Analog-to-digital converter (ADC),Phase detector,Tri-level resistor digital-to-analog converter | Journal | 110 |
ISSN | Citations | PageRank |
0026-2692 | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jue Wang | 1 | 0 | 0.34 |
| Xu Cheng | 2 | 8 | 3.89 |
| Jun Han | 3 | 0 | 0.34 |
| Xiaoyang Zeng | 4 | 442 | 107.26 |