Title
An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation
Abstract
This paper presents an energy-efficient deep neural network (DNN) training processor through the four key features: 1) Layer-wise Adaptive bit-Precision Scaling (LAPS) with 2) In-Out Slice Skipping (IOSS) core, 3) double-buffered Reconfigurable Accumulation Network (RAN), 4) momentum-ADAM unified OPTimizer Core (OPTC). Thanks to the bit-slice-level scalability and zero-slice skipping, it shows 5.9...
Year
DOI
Venue
2021
10.1109/COOLCHIPS52128.2021.9410324
2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
DocType
ISSN
ISBN
Conference
2473-4683
978-1-6654-1503-3
Citations 
PageRank 
References 
0
0.34
0
Authors
7
Name
Order
Citations
PageRank
Donghyeon Han13910.66
Dongseok Im2126.21
Gwangtae Park3203.41
Youngwoo Kim400.34
Seokchan Song500.34
Juhyoung Lee631.40
Hoi-Jun Yoo700.34