Paper Info
Title
Design Automation for Tree-based Nearest Neighborhood–aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion
Abstract
AbstractCellular Automata (CA) is attractive for high-speed VLSI implementation due to modularity, cascadability, and locality of interconnections confined to neighboring logic cells. However, this outcome is not easily transferable to tree-structured CA, since the neighbors having half and double the index value of the current CA cell under question can be sufficiently distanced apart on the FPGA floor. Challenges to meet throughput requirements, seamlessly translate algorithmic modifications for changing application specifications to gate level architectures and to address reliability challenges of semiconductor chips are ever increasing. Thus, a proper design framework assisting automation of synthesizable, delay-optimized VLSI architecture descriptions facilitating testability is desirable. In this article, we have automated the generation of hardware description of tree-structured CA that includes a built-in scan path realized with zero area and delay overhead. The scan path facilitates seeding the CA, state modification, and fault localization on the FPGA fabric. Three placement algorithms were proposed to ensure maximum physical adjacency amongst neighboring CA cells, arranged in a multi-columnar fashion on the FPGA grid. Our proposed architectures outperform implementations arising out of standard placers and behavioral designs, existing tree mapping strategies, and state-of-the-art FPGA centric error detection architectures in area and speed.
Year
DOI
Venue
2021
10.1145/3446206
ACM Transactions on Design Automation of Electronic Systems
Keywords
DocType
Volume
Cellular automata, FPGA, look-up table, placement, design automation, scan path
Journal
26
Issue
ISSN
Citations 
4
1084-4309
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Ayan Palchaudhuri1117.67
Sandeep Sharma2126.21
Anindya Sundar Dhar39726.09