Name
Abstract | ||
|---|---|---|
3D integration technologies are becoming increasingly viable to mitigate the limitations and slowdown in traditional 2D transistor scaling. 3D-Split SRAMs, realized by splitting the bitlines (BL) and/or wordlines (WL) across two or more 3D-arranged tiers, promise improved power/performance due to reduced RC parasitics. However, their feasibility and efficacy depend on the pitch and RC parasitics o... |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/CICC51472.2021.9431528 | 2021 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | DocType | ISBN |
Wafer bonding,Three-dimensional displays,Conferences,Random access memory,Prototypes,Performance gain,Gain measurement | Conference | 978-1-7281-7581-2 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
16 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. Mathur | 1 | 0 | 0.34 |
| M. Bhargava | 2 | 0 | 0.34 |
| H. Perry | 3 | 0 | 0.34 |
| A. Cestero | 4 | 0 | 0.34 |
| F. Frederick | 5 | 0 | 0.34 |
| S. Hung | 6 | 0 | 0.34 |
| C. Chao | 7 | 0 | 0.34 |
| D. Smith | 8 | 0 | 0.34 |
| D. Fisher | 9 | 0 | 0.34 |
| N. Robson | 10 | 0 | 0.34 |
| X. Xu | 11 | 0 | 0.34 |
| P. Chandupatla | 12 | 0 | 0.34 |
| R. Balachandran | 13 | 0 | 0.34 |
| Saurabh Sinha | 14 | 195 | 21.88 |
| B. Cline | 15 | 0 | 0.34 |
| J. P. Kulkarni | 16 | 0 | 0.34 |