Name
Title | ||
|---|---|---|
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips |
Abstract | ||
|---|---|---|
True random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases, including security-critical cryptographic primitives, scientific simulations, machine learning applications, and even recreational entertainment. Unfortunately, not every computing system is equipped with dedicated TRNG hardware, limiting the application space and security guarantees for such systems. To open the application space and enable security guarantees for the overwhelming majority of computing systems that do not necessarily have dedicated TRNG hardware (e.g., processing-in-memory systems), we develop QUAC-TRNG, a new high-throughput TRNG that can be fully implemented in commodity DRAM chips, which are key components in most modern systems.QUAC-TRNG exploits the new observation that a carefully-engineered sequence of DRAM commands activates four consecutive DRAM rows in rapid succession. This QUadruple ACtivation (QUAC) causes the bitline sense amplifiers to non-deterministically converge to random values when we activate four rows that store conflicting data because the net deviation in bitline voltage fails to meet reliable sensing margins.We experimentally demonstrate that QUAC reliably generates random values across 136 commodity DDR4 DRAM chips from one major DRAM manufacturer. We describe how to develop an effective TRNG (QUAC-TRNG) based on QUAC. We evaluate the quality of our TRNG using the commonly-used NIST statistical test suite for randomness and find that QUAC-TRNG successfully passes each test. Our experimental evaluations show that QUAC-TRNG reliably generates true random numbers with a throughput of 3.44 Gb/s (per DRAM channel), outperforming the state-of-the-art DRAM-based TRNG by 15.08× and 1.41× for basic and throughput-optimized versions, respectively. We show that QUAC-TRNG utilizes DRAM bandwidth better than the state-of-the-art, achieving up to 2.03× the throughput of a throughput-optimized baseline when scaling bus frequencies to 12 GT/s. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISCA52012.2021.00078 | 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) |
Keywords | DocType | ISSN |
scaling bus frequencies,throughput-optimized versions,NIST statistical test suite,DRAM manufacturer,bitline sense amplifier,quadruple activation,carefully-engineered sequence,TRNG hardware,machine learning applications,security-critical cryptographic primitives,random physical process,high-throughput true random number generation,four consecutive DRAM rows,DDR4 DRAM chips,DRAM-based TRNG,QUAC-TRNG,security guarantees,application space,dedicated TRNG hardware,quadruple row activation,commodity DRAM chips,high-throughput TRNG,processing-in-memory systems | Conference | 1063-6897 |
ISBN | Citations | PageRank |
978-1-6654-3334-1 | 7 | 0.37 |
References | Authors | |
0 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ataberk Olgun | 1 | 14 | 3.47 |
| Minesh Patel | 2 | 204 | 9.82 |
| A. Giray Yağlıkçı | 3 | 11 | 1.40 |
| Haocong Luo | 4 | 13 | 1.78 |
| Jeremie Kim | 5 | 263 | 13.68 |
| Nisa Bostancı | 6 | 7 | 0.37 |
| Nandita Vijaykumar | 7 | 44 | 2.35 |
| Oğuz Ergin | 8 | 50 | 3.58 |
| Onur Mutlu | 9 | 9446 | 357.40 |