Name
Title | ||
|---|---|---|
A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC |
Abstract | ||
|---|---|---|
This paper presents a Track and Hold sampling buffer topology, which allows sampling the signal inside the buffer itself while achieving very high linearity. The circuit operations and its large-signal behavior are analyzed and the key design strategies to maximize linearity are discussed. Then, a 60 GS/s, 52.6 dB SFDR, 8 ways interleaved simulated prototype in TSMC 5 nm technology, consuming 2.52 mW from a 0.9 V supply, is compared to the state-of-the-art sampling buffers, showing linearity improvement. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISCAS51556.2021.9401618 | 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
Keywords | DocType | ISSN |
Analog-to-digital converter, Track and Hold, Buffer, Sampler | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alessio Di Pasquo | 1 | 0 | 0.34 |
| Claudio Nani | 2 | 0 | 0.34 |
| Enrico Monaco | 3 | 0 | 0.34 |
| L. Fanucci | 4 | 167 | 17.90 |