Name
Abstract | ||
|---|---|---|
In this paper a low-voltage, high speed frequency divider architecture exploiting the Folded MOS Current Mode Logic (FMCML) and an analytical design strategy to optimize its performance are presented. To validate the proposed models and design procedures we have used a 28nm, Fully Depleted Silicon on Insulator (FDSOI), CMOS technology to design and simulate a divide-by-8 circuit. The designed frequency divider exhibits a maximum operating frequency of about 15GHz with a power consumption of only 110.W thus confirming the advantages of the proposed approach. |
Year | DOI | Venue |
|---|---|---|
2021 | 10.1109/ISCAS51556.2021.9401445 | 2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
DocType | ISSN | Citations |
Conference | 0271-4302 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Francesco Centurelli | 1 | 56 | 15.93 |
| giuseppe scotti | 2 | 308 | 39.14 |
| Alessandro Trifiletti | 3 | 0 | 0.34 |
| Gaetano Palumbo | 4 | 708 | 106.77 |